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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-02 08:56:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 13:00:56 +0100
commite25b5ef39fd10e48e87e0c4770a721a786e36a36 (patch)
tree113c2b4eba9bf7fddd6badbafc3c0f6ac0cef04f /src/northbridge/via
parent3d15e10aef5811e8c7146e5defb0e36b848547ed (diff)
downloadcoreboot-e25b5ef39fd10e48e87e0c4770a721a786e36a36.tar.xz
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/via')
-rw-r--r--src/northbridge/via/vx900/Kconfig4
-rw-r--r--src/northbridge/via/vx900/northbridge.c5
2 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 73d40adfba..4b1e6cc4cd 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -33,6 +33,10 @@ config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
+config MMCONF_BUS_NUMBER
+ int
+ default 256
+
config VGA_BIOS_ID
string
default "1106,7122"
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index a4a8ecec48..7429c4f973 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -297,10 +297,7 @@ static void vx900_read_resources(device_t dev)
/* Now do the same for our MMCONF
* We always run with MMCONF enabled. We need to access the extended
* config space when configuring PCI-Express links */
- res = new_resource(dev, idx++);
- res->size = 256 * MiB;
- res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ mmconf_resource(dev, idx++);
pci_domain_read_resources(dev);
}