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authorRonald G. Minnich <rminnich@gmail.com>2003-09-30 02:16:47 +0000
committerRonald G. Minnich <rminnich@gmail.com>2003-09-30 02:16:47 +0000
commit99dcf231f48433a07cbd47ecb0c23301a6b5b34e (patch)
tree0ea4045b3c64e80081c15a706c9308a5b94c4ba6 /src/northbridge/via
parent02360d6672bd95b980f83f464dea4c624b8f8aa2 (diff)
downloadcoreboot-99dcf231f48433a07cbd47ecb0c23301a6b5b34e.tar.xz
The epia now works.
Now to fix the ram ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via')
-rw-r--r--src/northbridge/via/vt8601/northbridge.c72
-rw-r--r--src/northbridge/via/vt8601/raminit.c2
2 files changed, 12 insertions, 62 deletions
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 33dc4ec758..8f5d1730a6 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -20,77 +20,27 @@ struct mem_range *sizeram(void)
device_t dev;
int i, idx;
-#warning "FIXME handle interleaved nodes"
- dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ dev = dev_find_slot(0, 0);
if (!dev) {
- printk_err("Cannot find PCI: 0:18.1\n");
+ printk_err("Cannot find PCI: 0:0\n");
return 0;
}
- mmio_basek = (dev_root.resource[1].base >> 10);
- /* Round mmio_basek to something the processor can support */
- mmio_basek &= ~((1 << 6) -1);
-
-#if 1
-#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
- /* Round the mmio hold to 256M */
- mmio_basek &= ~((256*1024) - 1);
-#endif
+ mem[0].basek = 0;
+ mem[0].sizek = 65536;
+ idx = 1;
+ while(idx < sizeof(mem)/sizeof(mem[0])) {
+ mem[idx].basek = 0;
+ mem[idx].sizek = 0;
+ idx++;
+ }
#if 1
- printk_debug("mmio_base: %dKB\n", mmio_basek);
-#endif
-
- for(idx = i = 0; i < 8; i++) {
- uint32_t base, limit;
- unsigned basek, limitk, sizek;
- base = pci_read_config32(dev, 0x40 + (i<<3));
- limit = pci_read_config32(dev, 0x44 + (i<<3));
- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
- continue;
- }
- basek = (base & 0xffff0000) >> 2;
- limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
- sizek = limitk - basek;
- if ((idx > 0) &&
- ((mem[idx -1].basek + mem[idx - 1].sizek) == basek)) {
- mem[idx -1].sizek += sizek;
- }
- else {
- mem[idx].basek = basek;
- mem[idx].sizek = sizek;
- idx++;
- }
- /* See if I need to split the region to accomodate pci memory space */
- if ((mem[idx - 1].basek <= mmio_basek) &&
- ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) {
- if (mem[idx - 1].basek < mmio_basek) {
- unsigned pre_sizek;
- pre_sizek = mmio_basek - mem[idx - 1].basek;
- mem[idx].basek = mmio_basek;
- mem[idx].sizek = mem[idx - 1].sizek - pre_sizek;
- mem[idx - 1].sizek = pre_sizek;
- idx++;
- }
- if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
- idx -= 1;
- }
- else {
- mem[idx - 1].basek = 4*1024*1024;
- mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
- }
- }
- }
-#if 0
for(i = 0; i < idx; i++) {
printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
i, mem[i].basek, i, mem[i].sizek);
}
#endif
- while(idx < sizeof(mem)/sizeof(mem[0])) {
- mem[idx].basek = 0;
- mem[idx].sizek = 0;
- idx++;
- }
+
return mem;
}
static void enumerate(struct chip *chip)
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index 7eba1cd51d..6f85189a60 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -371,7 +371,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
0x0000, 0x8088, 0xe0ee,
0xffff // end mark
};
- static cont uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
+ static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x56, 0x57};
device_t north = 0;