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authorPatrick Georgi <patrick@georgi-clan.de>2012-10-05 21:54:38 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-10-08 21:23:08 +0200
commit9aeb69447d3839675b2cac51c3e95a4724fd9b0d (patch)
treed9b1cc7483a51ab340d6d9fae78a30e562f99767 /src/northbridge/via
parentec2c18ee6068ef6adf6f5be437d7047c91773654 (diff)
downloadcoreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.tar.xz
hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/northbridge/via')
-rw-r--r--src/northbridge/via/cx700/Kconfig15
-rw-r--r--src/northbridge/via/cx700/lpc.c3
2 files changed, 15 insertions, 3 deletions
diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
index 7e4a193ab5..8f6e3374e9 100644
--- a/src/northbridge/via/cx700/Kconfig
+++ b/src/northbridge/via/cx700/Kconfig
@@ -28,6 +28,8 @@ config CX700_VIDEO_MB_128MB
endchoice
+if NORTHBRIDGE_VIA_CX700
+
config VIDEO_MB
int
default 0 if CX700_VIDEO_MB_OFF
@@ -36,5 +38,16 @@ config VIDEO_MB
default 32 if CX700_VIDEO_MB_32MB
default 64 if CX700_VIDEO_MB_64MB
default 128 if CX700_VIDEO_MB_128MB
- depends on NORTHBRIDGE_VIA_CX700
+config HPET_ADDRESS_OVERRIDE
+ def_bool y
+
+config HPET_ADDRESS
+ hex
+ default 0xfe800000
+
+config HPET_MIN_TICKS
+ hex
+ default 0x90
+
+endif
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 77ab97c145..5a9ced0247 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -32,7 +32,6 @@
#include <stdlib.h>
#define ACPI_IO_BASE 0x400
-#define HPET_ADDR 0xfe800000UL
static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
@@ -229,7 +228,7 @@ static void cx700_set_lpc_registers(struct device *dev)
pci_write_config8(dev, 0x40, 0x54);
/* Enable HPET timer */
- pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8));
+ pci_write_config32(dev, 0x68, (1 << 31) | (CONFIG_HPET_ADDRESS >> 8));
}