diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-07 15:40:26 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-07 15:40:26 +0000 |
commit | 56a684a2ee52b765fc69ec8c922c3da9d8ab7430 (patch) | |
tree | a8b4c74a857d8f09e071c0aebbbe887327ab24c6 /src/northbridge/via | |
parent | eea66b7c3534d2959be482fc97b84d656c5bb953 (diff) | |
download | coreboot-56a684a2ee52b765fc69ec8c922c3da9d8ab7430.tar.xz |
- copy_and_run() gets the same calling convention on AMD and on all the others.
- some vx800 Kconfig fixes
- remove warnings...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via')
-rw-r--r-- | src/northbridge/via/vx800/northbridge.c | 5 | ||||
-rw-r--r-- | src/northbridge/via/vx800/pci_rawops.h | 235 | ||||
-rw-r--r-- | src/northbridge/via/vx800/vx800_ide.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx800/vx800_lpc.c | 15 |
4 files changed, 136 insertions, 121 deletions
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 5533a4fda3..4dfe843bae 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -142,7 +142,6 @@ static void pci_domain_set_resources(device_t dev) * this register's value multiply 64 * 1024 * 1024 */ for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - unsigned char reg; rambits = pci_read_config8(mc_dev, ramregs[i]); if (rambits != 0) break; @@ -179,7 +178,7 @@ if register with invalid value we set frame buffer size to 32M for default, but assign_resources(&dev->link[0]); } -static const struct device_operations pci_domain_ops = { +static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, @@ -196,7 +195,7 @@ static void cpu_bus_noop(device_t dev) { } -static const struct device_operations cpu_bus_ops = { +static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h index d7646d550f..d0aa392a5a 100644 --- a/src/northbridge/via/vx800/pci_rawops.h +++ b/src/northbridge/via/vx800/pci_rawops.h @@ -26,243 +26,260 @@ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x07) << 12)) -struct VIA_PCI_REG_INIT_TABLE { + +struct VIA_PCI_REG_INIT_TABLE { u8 ChipRevisionStart; u8 ChipRevisionEnd; u8 Bus; u8 Device; u8 Function; - u32 Register; + u32 Register; u8 Mask; u8 Value; }; -typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ +typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ - uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where) +u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); //seg == 0 #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inb(0xCFC + (addr & 3)); } -#if MMCONF_SUPPORT - uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read8x(addr); + unsigned addr; + addr = dev | where; + return read8x(addr); } #endif - uint8_t pci_rawread_config8(device_t_raw dev, unsigned where) +u8 pci_rawread_config8(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config8(dev, where); #else return pci_io_rawread_config8(dev, where); #endif } - uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where) +u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); } -#if MMCONF_SUPPORT - uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read16x(addr); + unsigned addr; + addr = dev | where; + return read16x(addr); } #endif - uint16_t pci_rawread_config16(device_t_raw dev, unsigned where) +u16 pci_rawread_config16(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config16(dev, where); #else - return pci_io_rawread_config16(dev, where); + return pci_io_rawread_config16(dev, where); #endif } - - uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where) +u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } -#if MMCONF_SUPPORT - uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read32x(addr); + unsigned addr; + addr = dev | where; + return read32x(addr); } #endif - uint32_t pci_rawread_config32(device_t_raw dev, unsigned where) +u32 pci_rawread_config32(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config32(dev, where); #else - return pci_io_rawread_config32(dev, where); + return pci_io_rawread_config32(dev, where); #endif } - void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); } -#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { - unsigned addr; - addr = dev | where; - write8x(addr, value); + unsigned addr; + addr = dev | where; + write8x(addr, value); } #endif - void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config8(dev, where, value); #else - pci_io_rawwrite_config8(dev, where, value); + pci_io_rawwrite_config8(dev, where, value); #endif } - - void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { - unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; + unsigned addr; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); } -#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, + u16 value) { - unsigned addr; - addr = dev | where; - write16x(addr, value); + unsigned addr; + addr = dev | where; + write16x(addr, value); } #endif - void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config16(dev, where, value); #else pci_io_rawwrite_config16(dev, where, value); #endif } - - void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } -#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, + u32 value) { - unsigned addr; - addr = dev | where; - write32x(addr, value); + unsigned addr; + addr = dev | where; + write32x(addr, value); } #endif - void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config32(dev, where, value); #else - pci_io_rawwrite_config32(dev, where, value); + pci_io_rawwrite_config32(dev, where, value); #endif } - -void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask) -{ u8 data=pci_rawread_config8(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config8(dev,where,data); +void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) +{ + u8 data = pci_rawread_config8(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config8(dev, where, data); } -void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask) -{ uint16_t data=pci_rawread_config16(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config16(dev,where,data); + +void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) +{ + u16 data = pci_rawread_config16(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config16(dev, where, data); } -void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask) -{ uint32_t data=pci_rawread_config32(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config32(dev,where,data); + +void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) +{ + u32 data = pci_rawread_config32(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config32(dev, where, data); } -void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask) +void io_rawmodify_config8(u16 where, u8 orval, u8 mask) { - u8 data=inb(where); - data&=(~mask); - data|=orval; - outb(data,where); + u8 data = inb(where); + data &= (~mask); + data |= orval; + outb(data, where); } -void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata) +void via_pci_inittable(u8 chipversion, + struct VIA_PCI_REG_INIT_TABLE *initdata) { - u8 i=0; + u8 i = 0; device_t_raw devbxdxfx; - for(i=0;;i++) { - if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0)) - break; - if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){ - devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function); - pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask); - } + for (i = 0;; i++) { + if ((initdata[i].Mask == 0) && (initdata[i].Value == 0) + && (initdata[i].Bus == 0) + && (initdata[i].ChipRevisionEnd == 0xff) + && (initdata[i].ChipRevisionStart == 0) + && (initdata[i].Device == 0) + && (initdata[i].Function == 0) + && (initdata[i].Register == 0)) + break; + if ((chipversion >= initdata[i].ChipRevisionStart) + && (chipversion <= initdata[i].ChipRevisionEnd)) { + devbxdxfx = + PCI_RAWDEV(initdata[i].Bus, initdata[i].Device, + initdata[i].Function); + pci_rawmodify_config8(devbxdxfx, + initdata[i].Register, + initdata[i].Value, + initdata[i].Mask); + } } } #endif diff --git a/src/northbridge/via/vx800/vx800_ide.c b/src/northbridge/via/vx800/vx800_ide.c index b4c40d4e2f..9fa8f35dbe 100644 --- a/src/northbridge/via/vx800/vx800_ide.c +++ b/src/northbridge/via/vx800/vx800_ide.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include "vx800.h" -static const idedevicepcitable[16 * 12] = { +static const u8 idedevicepcitable[16 * 12] = { /* 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6, diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c index 7a74b65d3d..874f32fbbd 100644 --- a/src/northbridge/via/vx800/vx800_lpc.c +++ b/src/northbridge/via/vx800/vx800_lpc.c @@ -104,7 +104,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); } -void setup_pm(device_t dev) +static void setup_pm(device_t dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -198,7 +198,7 @@ void setup_pm(device_t dev) */ } -void S3_ps2_kb_ms_wakeup(struct device *dev) +static void S3_ps2_kb_ms_wakeup(struct device *dev) { u8 enables; enables = pci_read_config8(dev, 0x51); @@ -222,12 +222,12 @@ void S3_ps2_kb_ms_wakeup(struct device *dev) } -void S3_usb_wakeup(struct device *dev) +static void S3_usb_wakeup(struct device *dev) { outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME } -void S3_lid_wakeup(struct device *dev) +static void S3_lid_wakeup(struct device *dev) { outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME } @@ -301,7 +301,7 @@ static void vx800_sb_init(struct device *dev) /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -void vx800_read_resources(device_t dev) +static void vx800_read_resources(device_t dev) { struct resource *resource; @@ -312,10 +312,9 @@ void vx800_read_resources(device_t dev) IORESOURCE_STORED; resource->size = 2; resource->base = 0x2e; - } -void vx800_set_resources(device_t dev) +static void vx800_set_resources(device_t dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -323,7 +322,7 @@ void vx800_set_resources(device_t dev) pci_dev_set_resources(dev); } -void vx800_enable_resources(device_t dev) +static void vx800_enable_resources(device_t dev) { /* vx800 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses). however it does control the isa bus and so |