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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-19 19:57:01 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-05-27 13:54:47 +0200 |
| commit | 70d92b9465b1edf646b25b89f1442f7107b5f1f6 (patch) | |
| tree | 8d0a39990358f3fd92b00f0e790b7667ca90fd1c /src/northbridge/via | |
| parent | ef8bb9136e9371753e50cb15b334c9d0f5c70930 (diff) | |
| download | coreboot-70d92b9465b1edf646b25b89f1442f7107b5f1f6.tar.xz | |
CBMEM: Clarify CBMEM_TOP_BACKUP function usage
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/northbridge/via')
| -rw-r--r-- | src/northbridge/via/cn700/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/cx700/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/early_vx900.c | 6 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/northbridge.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 141ad150ad..2121162348 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); + set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 670603bae3..19bdf11bac 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } - set_top_of_ram(tolmk * 1024); + set_late_cbmem_top(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 6e1bc23cae..b350ffde28 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -18,10 +18,10 @@ #include <arch/io.h> #include <console/console.h> -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { - u16 reg_tom = pci_read_config8(MCU, 0x88); - return (((unsigned long)reg_tom) << 24) - (256 << 20); + u8 reg_tom = pci_read_config8(MCU, 0x88); + return (reg_tom << 24) - 256 * MiB; } /** diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 7429c4f973..fbb8fdf898 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -277,7 +277,7 @@ static void vx900_set_resources(device_t dev) u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); - set_top_of_ram(tolmk << 10); + set_late_cbmem_top(tolmk << 10); printk(BIOS_DEBUG, "======================================================\n"); assign_resources(dev->link_list); |