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authorElyes HAOUAS <ehaouas@noos.fr>2018-11-26 22:53:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:45 +0000
commit6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch)
treea95ac78c1e4e222971ee9749e9e114494681e9c4 /src/northbridge/via
parent1a5ce95815210032783d01e830390ee5b6a54dc5 (diff)
downloadcoreboot-6df3b64c77a868ab8526b980561ed2be3fe392b6.tar.xz
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/northbridge/via')
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 1d05fa731c..7acab31247 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -572,7 +572,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
printram("Selected DRAM frequency: %u MHz\n", val32);
/* Find CAS and CWL latencies */
- val = CEIL_DIV(ctrl->tAA, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
printram("Minimum CAS latency : %uT\n", val);
/* Find lowest supported CAS latency that satisfies the minimum value */
while (!((ctrl->cas_supported >> (val - 4)) & 1)
@@ -591,30 +591,30 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */
- val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
printram("Selected tRCD : %uT\n", val);
reg8 = ((val - 4) & 0x7) << 4;
/* Find tRP */
- val = CEIL_DIV(ctrl->tRP, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
printram("Selected tRP : %uT\n", val);
reg8 |= ((val - 4) & 0x7);
pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */
- val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
printram("Selected tRAS : %uT\n", val);
reg8 = ((val - 15) & 0x7) << 4;
/* Find tWR */
- ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);
+ ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
printram("Selected tWR : %uT\n", ctrl->WR);
reg8 |= ((ctrl->WR - 4) & 0x7);
pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */
- tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);
+ tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
printram("Selected tFAW : %uT\n", tFAW);
/* Find tRRD */
- tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);
+ tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
printram("Selected tRRD : %uT\n", tRRD);
val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */
reg8 = ((val - 0) & 0x7) << 4;
@@ -622,11 +622,11 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc3, reg8);
/* Find tRTP */
- val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
printram("Selected tRTP : %uT\n", val);
reg8 = ((val & 0x3) << 4);
/* Find tWTR */
- val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
printram("Selected tWTR : %uT\n", val);
reg8 |= ((val - 2) & 0x7);
pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
@@ -639,7 +639,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
* Since we previously set RxC4[7]
*/
reg8 = pci_read_config8(MCU, 0xc5);
- val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
printram("Minimum tRFC : %uT\n", val);
if (val < 30) {
val = 0;
@@ -652,7 +652,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */
- val = CEIL_DIV(ctrl->tRC, ctrl->tCK);
+ val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
printram("Required tRC : %uT\n", val);
}