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Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 20 insertions, 20 deletions

diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c
index 64680c5e28..159b2a4273 100644
--- a/src/northbridge/via/vx900/early_host_bus_ctl.c
+++ b/src/northbridge/via/vx900/early_host_bus_ctl.c
@@ -20,9 +20,9 @@ static void vx900_cpu_bus_preram_setup(void)
 {
 	/* Faster CPU to DRAM Cycle */
 	pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08);
-	/* CPU Interface Control – Basic Options */
+	/* CPU Interface Control - Basic Options */
 	pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c);
-	/*CPU Interface Control – Advanced Options */
+	/*CPU Interface Control - Advanced Options */
 	pci_write_config8(HOST_BUS, 0x52, 0xc7);
 	/* Enable 8QW burst and 4QW request merging [4] and [2]
 	 * and special mode for read cycles bit[3] */
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index e0c557936d..f4b61de88b 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -186,14 +186,14 @@ static pci_reg8 mcu_drv_ctrl_config[] = {
 	{0xd4, 0x80},		/* Set internal ODT to dynamically turn on or off */
 	{0xd6, 0x20},		/* Enable strong driving for MA and DRAM commands */
 	{0xd0, 0x88},		/* (ODT) Strength ?has effect? */
-	{0xe0, 0x88},		/* DRAM Driving – Group DQS (MDQS) */
+	{0xe0, 0x88},		/* DRAM Driving - Group DQS (MDQS) */
 	{0xe1, 0x00},		/* Disable offset mode for driving strength control */
-	{0xe2, 0x88},		/* DRAM Driving – Group DQ (MD, MDQM) */
-	{0xe4, 0xcc},		/* DRAM Driving – Group CSA (MCS, MCKE, MODT) */
-	{0xe8, 0x88},		/* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */
-	{0xe6, 0xff},		/* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */
-	{0xe7, 0xff},		/* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */
-	{0xe4, 0xcc},		/* DRAM Driving – Group CSA (MCS, MCKE, MODT) */
+	{0xe2, 0x88},		/* DRAM Driving - Group DQ (MD, MDQM) */
+	{0xe4, 0xcc},		/* DRAM Driving - Group CSA (MCS, MCKE, MODT) */
+	{0xe8, 0x88},		/* DRAM Driving - Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */
+	{0xe6, 0xff},		/* DRAM Driving - Group DCLK0 (DCLK[2:0] for DIMM0) */
+	{0xe7, 0xff},		/* DRAM Driving - Group DCLK1 (DCLK[5:3] for DIMM1) */
+	{0xe4, 0xcc},		/* DRAM Driving - Group CSA (MCS, MCKE, MODT) */
 	{0x91, 0x08},		/* MCLKO Output Phase Delay - I */
 	{0x92, 0x08},		/* MCLKO Output Phase Delay - II */
 	{0x93, 0x16},		/* CS/CKE Output Phase Delay */
@@ -807,8 +807,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
 	/* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
 	pci_mod_config8(MCU, 0x6b, 0x07, 0x03);	/* MSR Enable */
 
-	/* Step 09 – Issue MR2 cycle. Read a double word from the address
-	 * depended on DRAM’s Rtt_WR and CWL settings. */
+	/* Step 09 - Issue MR2 cycle. Read a double word from the address
+	 * depended on DRAM's Rtt_WR and CWL settings. */
 	mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl);
 	if (ma_swap)
 		mrs = ddr3_mrs_mirror_pins(mrs);
@@ -816,7 +816,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
 	printram("MR2: %.5x\n", mrs);
 	udelay(1000);
 
-	/* Step 10 – Issue MR3 cycle. Read a double word from the address 60000h
+	/* Step 10 - Issue MR3 cycle. Read a double word from the address 60000h
 	 * to set DRAM to normal operation mode. */
 	mrs = ddr3_get_mr3(0);
 	if (ma_swap)
@@ -825,8 +825,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
 	printram("MR3: %.5x\n", mrs);
 	udelay(1000);
 
-	/* Step 11 –Issue MR1 cycle. Read a double word from the address
-	 * depended on DRAM’s output driver impedance and Rtt_Nom settings.
+	/* Step 11 -Issue MR1 cycle. Read a double word from the address
+	 * depended on DRAM's output driver impedance and Rtt_Nom settings.
 	 * The DLL enable field, TDQS field, write leveling enable field,
 	 * additive latency field and Qoff field should be set to 0. */
 	mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom,
@@ -839,7 +839,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
 	udelay(1000);
 
 	/* Step 12 - Issue MR0 cycle. Read a double word from the address
-	 * depended on DRAM’s burst length, CAS latency and write recovery time
+	 * depended on DRAM's burst length, CAS latency and write recovery time
 	 * settings.
 	 * The read burst type field should be set to interleave.
 	 * The mode field should be set to normal mode.
@@ -942,13 +942,13 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
 		vx900_map_pr_vr(i, 3);
 	}
 
-	/* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
+	/* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
 	pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
 
 	/* Set BA[0/1/2] to [A13/14/15] */
 	vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP);
 
-	/* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
+	/* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
 	pci_mod_config8(MCU, 0x69, 0x00, (1 << 0));
 
 	printram("DIMM initialization sequence complete\n");
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 98e4bd2f00..e0a54bdaee 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -199,7 +199,7 @@ static void vx900_sata_init(device_t dev)
 	/* Resend COMRESET When Recovering SATA Gen2 Device Error */
 	pci_mod_config8(dev, 0x62, 1 << 1, 1 << 7);
 
-	/* Fix "PMP Device Can’t Detect HDD Normally" (VIA Porting Guide)
+	/* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide)
 	 * SATA device detection will not work unless we clear these bits.
 	 * Without doing this, SeaBIOS (and potentially other payloads) will
 	 * timeout when detecting SATA devices */
@@ -211,8 +211,8 @@ static void vx900_sata_init(device_t dev)
 	 * reset and check the BSY bit of one port only, and the BSY bit of
 	 * other port would be 1, then it does another software reset
 	 * immediately and causes the system hang.
-	 * This is because the first software reset doesn’t finish, and the
-	 * state machine of the host controller conflicts, it can’t finish the
+	 * This is because the first software reset doesn't finish, and the
+	 * state machine of the host controller conflicts, it can't finish the
 	 * second one anymore. The BSY bit of slave port would be always 1 after
 	 * the second software reset issues. BIOS should set the following
 	 * bit to avoid this issue. */