diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-24 14:03:29 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-31 23:33:43 +0000 |
| commit | 028b8e440b6c2fd0256535df486976b683b36fd4 (patch) | |
| tree | 201a01671b635d26622540f18be108a277a770be /src/northbridge | |
| parent | 42d52947934f20e419e42958ffb4973727a12e9c (diff) | |
| download | coreboot-028b8e440b6c2fd0256535df486976b683b36fd4.tar.xz | |
nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.
Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 5c9ef744b1..99621c293b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -418,6 +418,22 @@ static void disable_devices(void) pci_write_config32(host_dev, DEVEN, deven); } +static void init_egress(void) +{ + /* VC0: Enable, ID0, TC0 */ + EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); + + /* No Low Priority Extended VCs, one Extended VC */ + EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); + + /* VC1: Enable, ID1, TC1 */ + EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); + + /* Poll the VC1 Negotiation Pending bit */ + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) + ; +} + static void northbridge_dmi_init(void) { const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); @@ -462,6 +478,7 @@ static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; + init_egress(); northbridge_dmi_init(); /* Enable Power Aware Interrupt Routing. */ |