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authorStefan Reinauer <stepan@coresystems.de>2010-01-16 18:31:34 +0000
committerStefan Reinauer <stepan@openbios.org>2010-01-16 18:31:34 +0000
commit0401bd89b6e7105ca597a221fdbe2a8b75c35296 (patch)
treeec342f9dcaae2619bcb06a57789a07328402ea71 /src/northbridge
parent9fe4d797a37671a65053add3f7cca27397db0b9b (diff)
downloadcoreboot-0401bd89b6e7105ca597a221fdbe2a8b75c35296.tar.xz
coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code. Additionally it drops the other 12 instances of IOAPIC setup code and makes the components use the generic code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/via/cx700/cx700_lpc.c96
1 files changed, 3 insertions, 93 deletions
diff --git a/src/northbridge/via/cx700/cx700_lpc.c b/src/northbridge/via/cx700/cx700_lpc.c
index 90e453945e..115d66c235 100644
--- a/src/northbridge/via/cx700/cx700_lpc.c
+++ b/src/northbridge/via/cx700/cx700_lpc.c
@@ -31,102 +31,11 @@
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#define ACPI_IO_BASE 0x400
#define HPET_ADDR 0xfe800000UL
-#define IOAPIC_ADDR 0xfec00000ULL
-
-#if CONFIG_IOAPIC
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
-};
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high, val;
- unsigned long ioapic_base = IOAPIC_ADDR;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
- unsigned long bsp_lapicid = lapicid();
-
- l = (unsigned long *)ioapic_base;
-
- /* Set APIC ADDR */
- l[0] = 0;
- val = l[4];
- l[4] = (val & 0xF0FFFF) | (2 << 24); // 2 == ID as programmed elsewhere. should be a define? XXX
-
- /* Set APIC to FSB message bus. */
- l[0] = 0x3;
- val = l[4];
- l[4] = (val & 0xFFFFFE) | 1;
-
- ioapicregvalues[0].value_high = bsp_lapicid << (56 - 32);
-
- printk_debug("IOAPIC: Bootstrap Processor Local APIC ID = %02x\n", bsp_lapicid);
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IOAPIC is not responding.\n");
- return;
- }
- printk_debug("IOAPIC: IRQ reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-#endif
static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
@@ -369,7 +278,8 @@ static void cx700_lpc_init(struct device *dev)
cx700_set_lpc_registers(dev);
#if CONFIG_IOAPIC
- setup_ioapic();
+#define IO_APIC_ID 2
+ setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
#endif
/* Initialize interrupts */