diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 11:40:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:27:19 +0000 |
| commit | 0ddc2459bcbea812227b3b8b4fa5019e9a27da11 (patch) | |
| tree | 367f582e37b85ddccd705b3f4637d091c8f7edfe /src/northbridge | |
| parent | 6b2be99eb1961b6fb0bf0723b7ebe5b084ce77fc (diff) | |
| download | coreboot-0ddc2459bcbea812227b3b8b4fa5019e9a27da11.tar.xz | |
nb/intel/pineview: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/pineview/hostbridge_regs.h | 56 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 50 |
2 files changed, 57 insertions, 49 deletions
diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h new file mode 100644 index 0000000000..b320b9e10f --- /dev/null +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __PINEVIEW_HOSTBRIDGE_REGS_H__ +#define __PINEVIEW_HOSTBRIDGE_REGS_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEG 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +#endif /* __PINEVIEW_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 7c41b4c24a..d557d22f2d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -19,55 +19,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78 - -#define GGC 0x52 /* GMCH Graphics Control */ - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D0F0 (1 << 0) -#define DEVEN_D1F0 (1 << 1) -#define DEVEN_D2F0 (1 << 3) -#define DEVEN_D2F1 (1 << 4) - -#ifndef BOARD_DEVEN -#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) -#endif /* BOARD_DEVEN */ - -#define PAM0 0x90 -#define PAM1 0x91 -#define PAM2 0x92 -#define PAM3 0x93 -#define PAM4 0x94 -#define PAM5 0x95 -#define PAM6 0x96 - -#define LAC 0x97 /* Legacy Access Control */ -#define REMAPBASE 0x98 -#define REMAPLIMIT 0x9a -#define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAMC 0x9e /* Extended System Management RAM Control */ - -#define TOM 0xa0 -#define TOUUD 0xa2 -#define GBSM 0xa4 -#define BGSM 0xa8 -#define TSEG 0xac -#define TOLUD 0xb0 /* Top of Low Used Memory */ -#define ERRSTS 0xc8 -#define ERRCMD 0xca -#define SMICMD 0xcc -#define SCICMD 0xce -#define CGDIS 0xd8 -#define SKPAD 0xdc /* Scratchpad Data */ -#define CAPID0 0xe0 -#define DEV0T 0xf0 -#define MSLCK 0xf4 -#define MID0 0xf8 -#define DEBUP0 0xfc +#include "hostbridge_regs.h" /* Device 0:1.0 PCI configuration space (PCI Express) */ |