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authorSven Schnelle <svens@stackframe.org>2011-04-10 07:41:56 +0000
committerSven Schnelle <svens@stackframe.org>2011-04-10 07:41:56 +0000
commit148a4f5681263a24408d5988261bb3fd6b3c647e (patch)
treeead2ec62e5fd71901ec77e5dbff24076b727f081 /src/northbridge
parent61aee5f4b1d596a0cb007e666df13094abed6d10 (diff)
downloadcoreboot-148a4f5681263a24408d5988261bb3fd6b3c647e.tar.xz
i945: improve get_top_of_ram()
The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/raminit.c28
1 files changed, 26 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 8b7ffa148b..a9e4a910e2 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -3192,9 +3192,33 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
unsigned long get_top_of_ram(void)
{
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+ u32 tom;
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
+ /* IGD enabled, get top of Memory from BSM register */
+ tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+ } else {
+ tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+ }
+
+ /* if TSEG enabled subtract size */
+ switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
+ case 0x01:
+ /* 1MB TSEG */
+ tom -= 0x10000;
+ break;
+ case 0x03:
+ /* 2MB TSEG */
+ tom -= 0x20000;
+ break;
+ case 0x05:
+ /* 8MB TSEG */
+ tom -= 0x80000;
+ break;
+ default:
+ /* TSEG either disabled or invalid */
+ break;
+ }
return (unsigned long) tom;
}