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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-27 14:32:20 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-28 21:15:02 +0000 |
| commit | 197a3c6cea86cb92c10c05c710dd4184c0e7ba72 (patch) | |
| tree | 06eecd01477d2e48c4ef04242982179c78286f01 /src/northbridge | |
| parent | 3b8deeefa500a79958b0dd3428e2919ecfb794b1 (diff) | |
| download | coreboot-197a3c6cea86cb92c10c05c710dd4184c0e7ba72.tar.xz | |
nb/intel/x4x: Avoid x4x.h header with romcc-bootblock
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/x4x/bootblock.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1dfdf19ea4..e733287e93 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -16,7 +16,10 @@ #include <device/pci_ops.h> #include "iomap.h" -#include "x4x.h" + +/* Just re-define these instead of including x4x.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 static void bootblock_northbridge_init(void) { |