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authorThomas Jourdan <thomas.jourdan@gmail.com>2009-07-01 17:01:17 +0000
committerMyles Watson <mylesgw@gmail.com>2009-07-01 17:01:17 +0000
commit1a692d817650068e2125036d25bbaf2f3e9ec876 (patch)
tree76d51c38f3f85a0a121a7f7bfa82db1deab3ed96 /src/northbridge
parent6c96517a132ce26f906c8e38e19ebaab8b736e9a (diff)
downloadcoreboot-1a692d817650068e2125036d25bbaf2f3e9ec876.tar.xz
Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i3100/i3100.h4
-rw-r--r--src/northbridge/intel/i3100/raminit.c6
-rw-r--r--src/northbridge/intel/i3100/reset_test.c20
3 files changed, 28 insertions, 2 deletions
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 2501aa28b5..727e48a63c 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -57,3 +57,7 @@
#define DEVPRES1_D0F1 (1 << 5)
#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
+
+/* DRC */
+#define DRC_NOECC_MODE (0 << 20)
+#define DRC_72BIT_ECC (1 << 20)
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index af0f5d57b5..5aa4d9ded6 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -963,8 +963,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
/* FSB 167 */
{{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
- /* N/A */
- {{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
+ /* FSB 200 DIMM 400 */
+ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
};
static const u32 dqs_data[] = {
@@ -1220,5 +1220,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
+#if CONFIG_USE_DCACHE_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
+#endif
}
diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c
new file mode 100644
index 0000000000..9cf4d89d7e
--- /dev/null
+++ b/src/northbridge/intel/i3100/reset_test.c
@@ -0,0 +1,20 @@
+/* Convert to C by yhlu */
+#define MCH_DRC 0x7c
+#define DRC_DONE (1 << 29)
+
+/* If I have already booted once skip a bunch of initialization */
+/* To see if I have already booted I check to see if memory
+ * has been enabled.
+ */
+static int bios_reset_detected(void)
+{
+ uint32_t dword;
+
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
+
+ if( (dword & DRC_DONE) != 0 ) {
+ return 1;
+ }
+
+ return 0;
+}