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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-19 08:52:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:57:27 +0000
commit1a9034cca606ad7e2c1202c190a329bd8821afb4 (patch)
tree7060879ec6bcddf8e4f283b9d18434420adbe132 /src/northbridge
parent75ebb6c5dfa25d0f642faf5b253290dfacc59033 (diff)
downloadcoreboot-1a9034cca606ad7e2c1202c190a329bd8821afb4.tar.xz
i945,ICH7: Write on RPFN only once
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write. Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/early_init.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 6bfa1c724c..be882de819 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -354,8 +354,6 @@ static void ich7_setup_dmi_rcrb(void)
RCBA32(HDD) = 0x0f000003;
RCBA32(RP5D) = 0x05000002;
- RCBA32(RPFN) = 0x00543210;
-
pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141);