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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 21:31:17 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:08:09 +0000 |
| commit | 1be9f5841dabd42a740fe23a77ea128fa8d0835d (patch) | |
| tree | fc6fc827590eb83ca9ceea1091b65c123a37f045 /src/northbridge | |
| parent | 6c8e4dd87b334140b0b30420389931caec3c1c22 (diff) | |
| download | coreboot-1be9f5841dabd42a740fe23a77ea128fa8d0835d.tar.xz | |
haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig option
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.
Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 6501bc41a8..952cc7b039 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -98,4 +98,12 @@ config RO_REGION_ONLY config INTEL_GMA_BCLV_OFFSET default 0x48254 +config ENABLE_DDR_2X_REFRESH + bool "Enable DRAM Refresh 2x support" + default n + help + When enabled, the memory controller will refresh the DRAM twice as often. + This probably only happens when the DRAM gets hot, but what MRC exactly + does when this setting is enabled has not been investigated. + endif diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index ca948132b3..42a2a56c66 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -52,6 +52,7 @@ void mainboard_romstage_entry(void) .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, }; |