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authorMike Banon <mikebdp2@gmail.com>2020-11-21 21:58:50 +0300
committerFelix Held <felix-coreboot@felixheld.de>2020-11-23 19:18:03 +0000
commit1e6a227f1001825f3a948b0734fe60dc0313a88c (patch)
treeb9e9e537493234973195b7f642279890282dfc18 /src/northbridge
parent58d0336ef382cf299923777e269d11fd9fadcfa1 (diff)
downloadcoreboot-1e6a227f1001825f3a948b0734fe60dc0313a88c.tar.xz
nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Follow the example of newer AMD code for Stoneyridge and Picasso. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/agesa/family15tn/pci_devs.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h
index 22ce8f5e95..56138433e3 100644
--- a/src/northbridge/amd/agesa/family15tn/pci_devs.h
+++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h
@@ -7,6 +7,16 @@
#define BUS0 0
+/* GNB Root Complex */
+#define GNB_DEV 0x0
+#define GNB_FUNC 0
+#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
+
+/* IOMMU */
+#define IOMMU_DEV 0x0
+#define IOMMU_FUNC 2
+#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
+
/* Graphics and Display */
#define GFX_DEV 0x1
#define GFX_FUNC 0