summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorDamien Zammit <damien@zamaudio.com>2016-01-18 16:39:51 +1100
committerMartin Roth <martinroth@google.com>2016-01-26 04:51:38 +0100
commit2cfab90baa2eca04f6a522b65ce23650e5af56ff (patch)
treebd29ad3ddda695bd83b12008bb97f9816f2ce27b /src/northbridge
parentb8f8cdbd9ea5a3fd5f73e40c63edc8f33f2b53f3 (diff)
downloadcoreboot-2cfab90baa2eca04f6a522b65ce23650e5af56ff.tar.xz
nb/intel/pineview: Increase MMCONF decoding to 256 busses
Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/pineview/acpi/pineview.asl2
-rw-r--r--src/northbridge/intel/pineview/bootblock.c4
2 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index d32a906835..dccbf49387 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 1c04c28b98..a67cc1aeb5 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -1,8 +1,10 @@
#include <arch/io.h>
#define PCIEXBAR 0x60
+#define MMCONF_256_BUSSES 16
+#define ENABLE 1
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
- CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
+ CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
}