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authorAngel Pons <th3fanbus@gmail.com>2020-07-22 11:15:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:26:46 +0000
commit3896576a165968031b624d4800496b2ca1479096 (patch)
tree1b552deb4c5df8bc2d48409384e2e39aa5580ec6 /src/northbridge
parentb278838fd29fe0a0561baad23f5d306ca1374919 (diff)
downloadcoreboot-3896576a165968031b624d4800496b2ca1479096.tar.xz
nb/intel/x4x: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/x4x/hostbridge_regs.h40
-rw-r--r--src/northbridge/intel/x4x/x4x.h34
2 files changed, 41 insertions, 33 deletions
diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h
new file mode 100644
index 0000000000..fea113f691
--- /dev/null
+++ b/src/northbridge/intel/x4x/hostbridge_regs.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __X4X_HOSTBRIDGE_REGS_H__
+#define __X4X_HOSTBRIDGE_REGS_H__
+
+#define D0F0_EPBAR_LO 0x40
+#define D0F0_EPBAR_HI 0x44
+#define D0F0_MCHBAR_LO 0x48
+#define D0F0_MCHBAR_HI 0x4c
+#define D0F0_GGC 0x52
+#define D0F0_DEVEN 0x54
+#define D0EN (1 << 0)
+#define D1EN (1 << 1)
+#define IGD0EN (1 << 3)
+#define IGD1EN (1 << 4)
+#define D3F0EN (1 << 6)
+#define D3F1EN (1 << 7)
+#define D3F2EN (1 << 8)
+#define D3F3EN (1 << 9)
+#define PEG1EN (1 << 13)
+#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN)
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+#define D0F0_DMIBAR_LO 0x68
+#define D0F0_DMIBAR_HI 0x6c
+#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/
+#define D0F0_REMAPBASE 0x98
+#define D0F0_REMAPLIMIT 0x9a
+#define D0F0_SMRAM 0x9d
+#define D0F0_ESMRAMC 0x9e
+#define D0F0_TOM 0xa0
+#define D0F0_TOUUD 0xa2
+#define D0F0_TOLUD 0xb0
+#define D0F0_GBSM 0xa4
+#define D0F0_BGSM 0xa8
+#define D0F0_TSEG 0xac
+#define D0F0_SKPD 0xdc /* Scratchpad Data */
+#define D0F0_CAPID0 0xe0
+
+#endif /* __X4X_HOSTBRIDGE_REGS_H__ */
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 5418b4141d..133f31d174 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -9,39 +9,7 @@
/*
* D0:F0
*/
-#define D0F0_EPBAR_LO 0x40
-#define D0F0_EPBAR_HI 0x44
-#define D0F0_MCHBAR_LO 0x48
-#define D0F0_MCHBAR_HI 0x4c
-#define D0F0_GGC 0x52
-#define D0F0_DEVEN 0x54
-#define D0EN (1 << 0)
-#define D1EN (1 << 1)
-#define IGD0EN (1 << 3)
-#define IGD1EN (1 << 4)
-#define D3F0EN (1 << 6)
-#define D3F1EN (1 << 7)
-#define D3F2EN (1 << 8)
-#define D3F3EN (1 << 9)
-#define PEG1EN (1 << 13)
-#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN)
-#define D0F0_PCIEXBAR_LO 0x60
-#define D0F0_PCIEXBAR_HI 0x64
-#define D0F0_DMIBAR_LO 0x68
-#define D0F0_DMIBAR_HI 0x6c
-#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/
-#define D0F0_REMAPBASE 0x98
-#define D0F0_REMAPLIMIT 0x9a
-#define D0F0_SMRAM 0x9d
-#define D0F0_ESMRAMC 0x9e
-#define D0F0_TOM 0xa0
-#define D0F0_TOUUD 0xa2
-#define D0F0_TOLUD 0xb0
-#define D0F0_GBSM 0xa4
-#define D0F0_BGSM 0xa8
-#define D0F0_TSEG 0xac
-#define D0F0_SKPD 0xdc /* Scratchpad Data */
-#define D0F0_CAPID0 0xe0
+#include "hostbridge_regs.h"
/*
* D1:F0 PEG