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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 19:10:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 12:07:12 +0000 |
| commit | 3b9d3e92c0dbdec5b6ee466fe4a80b2eef417328 (patch) | |
| tree | 44cd6dd8bcd12df5c6f78d83f2fa90e269054c60 /src/northbridge | |
| parent | b50ca574efbb1061343eaeab715c2076f62b1a3e (diff) | |
| download | coreboot-3b9d3e92c0dbdec5b6ee466fe4a80b2eef417328.tar.xz | |
nb/intel/sandybridge: Fix typo in comment
Change-Id: I8271911695f41ef7cac1bb228309af0568e5bb0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index e23753a0b1..57c28fc9f4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -4238,7 +4238,7 @@ void channel_scrub(ramctr_timing *ctrl) * The following loops writes to every DRAM address, setting the ECC bits to the * correct value. A read from this location will no longer return a CRC error, * except when a bit has toggled due to external events. - * The same could be accieved by writing to the physical memory map, but it's + * The same could be achieved by writing to the physical memory map, but it's * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, * and firmware running in x86_32. */ |