diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2017-10-31 09:42:46 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-15 00:45:33 +0000 |
| commit | 6dd2f69878112cb4c0512e4b91088c7a6f1ac6a3 (patch) | |
| tree | 61f109492b69a8b7016f82e6ed10dc3a163630d2 /src/northbridge | |
| parent | fd470f7163709c1022ee6185134a2387812774ec (diff) | |
| download | coreboot-6dd2f69878112cb4c0512e4b91088c7a6f1ac6a3.tar.xz | |
vx900: map the SPI controller
This is required for Flashrom to work well.
Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/via/vx900/lpc.c | 51 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/vx900.h | 2 |
2 files changed, 51 insertions, 2 deletions
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index b36aaed1b0..43e4d4c3b0 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -184,9 +184,56 @@ static void vx900_lpc_init(device_t dev) dump_pci_device(dev); } +static void vx900_lpc_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + /* MMIO space */ + res = new_resource(dev, VX900_MMCONFIG_MBAR); + res->size = 0x1000; + res->align = 12; + res->gran = 12; + res->limit = 0xffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; + + /* SPI controller */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->size = 0x8; + res->align = 12; + res->gran = 12; + res->limit = 0xffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; +} + +static void vx900_lpc_set_resources(device_t dev) +{ + struct resource *mmio, *spi; + u32 reg; + + mmio = find_resource(dev, VX900_MMCONFIG_MBAR); + if (mmio) { + report_resource_stored(dev, mmio, "<mmconfig>"); + mmio->flags |= IORESOURCE_STORED; + reg = pci_read_config32(dev, VX900_MMCONFIG_MBAR); + reg &= 0xff000000; + reg |= mmio->base >> 8; + pci_write_config32(dev, VX900_MMCONFIG_MBAR, reg); + + spi = find_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + if (spi) { + report_resource_stored(dev, spi, "<spi>"); + spi->flags |= IORESOURCE_STORED; + /* Set base and the enable bit. */ + ((u32*)(uintptr_t)mmio->base)[0] = (spi->base | 0x01); + } + } + pci_dev_set_resources(dev); +} + static struct device_operations vx900_lpc_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = vx900_lpc_read_resources, + .set_resources = vx900_lpc_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, .scan_bus = scan_lpc_bus, diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 12e5733e61..216f63783e 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -26,6 +26,8 @@ #define SMBUS_IO_BASE 0x500 +#define VX900_MMCONFIG_MBAR 0xbc + /* The maximum number of DIMM slots that the VX900 supports */ #define VX900_MAX_DIMM_SLOTS 2 #define VX900_MAX_MEM_RANKS 4 |