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authorAngel Pons <th3fanbus@gmail.com>2020-11-13 13:38:04 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-19 23:04:05 +0000
commit868bca2527da30f6974b1f5a61c8a5b55620a630 (patch)
tree31c352ca096321a991ffc061cf8e86a95e8f81b6 /src/northbridge
parentdca3cb572bb2f506b8ec57bb7e6017b0b5e8acf2 (diff)
downloadcoreboot-868bca2527da30f6974b1f5a61c8a5b55620a630.tar.xz
nb/intel/sandybridge: Clean up `dram_mr2` function
Constify variables, and also remove pointless and-masks on mr2reg. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3829012ff7d41f4308ee84d6fbf3b1f2803431af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c21
1 files changed, 9 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 453222e59d..3ed1a3a335 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -757,22 +757,19 @@ static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel)
static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel)
{
- u16 pasr, cwl, mr2reg;
- odtmap odt;
- int srt = 0;
-
- pasr = 0;
- cwl = ctrl->CWL - 5;
- odt = get_ODT(ctrl, channel);
+ const u16 pasr = 0;
+ const u16 cwl = ctrl->CWL - 5;
+ const odtmap odt = get_ODT(ctrl, channel);
+ int srt = 0;
if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ)
srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh;
- mr2reg = 0;
- mr2reg = (mr2reg & ~0x07) | pasr;
- mr2reg = (mr2reg & ~0x38) | (cwl << 3);
- mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6);
- mr2reg = (mr2reg & ~0x80) | (srt << 7);
+ u16 mr2reg = 0;
+ mr2reg |= pasr;
+ mr2reg |= cwl << 3;
+ mr2reg |= ctrl->auto_self_refresh << 6;
+ mr2reg |= srt << 7;
mr2reg |= (odt.rttwr / 60) << 9;
write_mrreg(ctrl, channel, rank, 2, mr2reg);