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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2018-12-25 13:21:03 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-12-28 06:39:14 +0000
commit8f537442d5d1014e333ed469d0e75a87f12cfbaf (patch)
treebc77defdf503e0aac59c1ab25718ab897fd303ed /src/northbridge
parent3b1a42f95d3f259f18b5f211dd112d03df9f78dd (diff)
downloadcoreboot-8f537442d5d1014e333ed469d0e75a87f12cfbaf.tar.xz
mb/google/hatch: Enable console UART
This patch incorporates following changes to enable console on UART0 1. update default console number to 0 2. Enable PCI port for UART0 GPIO configuration will be done by coreboot based on correct console number. Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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