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| author | Li-Ta Lo <ollie@lanl.gov> | 2006-04-19 15:11:01 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-04-19 15:11:01 +0000 |
| commit | 965b5ad85bf8f7ab144f81c232fd40e320c22545 (patch) | |
| tree | 2459f430b2c1570ef98ef79a9dc83b5ecbb9d99d /src/northbridge | |
| parent | 36c00aa39b9374fbf5f762fb9ebb022bce1f7fa0 (diff) | |
| download | coreboot-965b5ad85bf8f7ab144f81c232fd40e320c22545.tar.xz | |
resolve conflict
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index ea54c49277..504658576d 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -125,6 +125,13 @@ static void pll_reset(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) { #if 0 + print_debug("MSR "); + print_debug_hex32(GLCP_SYS_RSTPLL); + print_debug("is "); + print_debug_hex32(msr.hi); + print_debug(":"); + print_debug_hex32(msr.lo); + msr.hi = PLLMSRhi; msr.lo = PLLMSRlo; wrmsr(GLCP_SYS_RSTPLL, msr); |