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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-19 22:49:50 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-08-21 19:54:13 +0200
commita60fb4d2dbd7748a92c5811f22e62575b1640998 (patch)
treecd9d47bbdc499c678e326eadeac7821d05ffa465 /src/northbridge
parent4f3873d2cec66d1b72577e3c516287f356af3f23 (diff)
downloadcoreboot-a60fb4d2dbd7748a92c5811f22e62575b1640998.tar.xz
i945: Remove GTT avoidance offset.
Not needed anymore with GTT at the end of range. Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6717 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/gma.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index e8a57b17c8..8b5b05387c 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -104,8 +104,6 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
u32 uma_size;
u16 reg16;
- pphysbase += 0x20000;
-
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n",
(void *)pgfx, pmmio, piobase, pphysbase);