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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-03 18:33:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:28:01 +0000 |
| commit | ac12976f0c411c1b337bf9a9619b2b54e81f362b (patch) | |
| tree | 8399b69e6dff9b30b9f1a0e1c18c2871ebea01de /src/northbridge | |
| parent | 6e98292821ad70ebf970d2ae90faa062d960a5bf (diff) | |
| download | coreboot-ac12976f0c411c1b337bf9a9619b2b54e81f362b.tar.xz | |
nb/intel/pineview: Fix clearing memory
The regions TSEG, GSM, GMS should not be marked as cacheable
resources.
Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index a04b62b5d5..e98c16bd92 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -98,9 +98,9 @@ static void mch_domain_read_resources(struct device *dev) /* Report the memory regions */ ram_resource(dev, index++, 0, 640); ram_resource(dev, index++, 768, tomk - 768); - reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); - reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); - reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + mmio_resource(dev, index++, tseg_basek, tseg_sizek); + mmio_resource(dev, index++, gtt_basek, gsm_sizek); + mmio_resource(dev, index++, igd_basek, gms_sizek); reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* |