code cleanup, comments added

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 49 insertions, 32 deletions

diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 97067d4e70..ff54d793bc 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -239,8 +239,7 @@ setup_gx2(void)
 }
 
 static void enable_shadow(device_t dev)
-{
-	
+{	
 }
 
 static void northbridge_init(device_t dev) 
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 77a2dce6cd..bbaf776564 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -263,11 +263,10 @@ GLIUInit(struct gliutable *gl){
 	while (gl->desc_type != GL_END){
 		switch(gl->desc_type){
 		default: 
-				printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported  type: ", __FUNCTION__, 
-							gl->desc_name, gl->desc_type, gl->hi, gl->hi);
-				printk_err("Must be %x, %x, %x, %x, %x, or %x\n", SC_SHADOW,R_SYSMEM,BMO_DMM,
-											BM_DMM, BMO_SMM,BM_SMM);
-	
+			printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported  type: ",
+				   __FUNCTION__, gl->desc_name, gl->desc_type, gl->hi, gl->hi);
+			printk_err("Must be %x, %x, %x, %x, %x, or %x\n",
+				   SC_SHADOW,R_SYSMEM,BMO_DMM, BM_DMM, BMO_SMM,BM_SMM);
 		case SC_SHADOW: /*  Check for a Shadow entry*/
 			ShadowInit(gl);
 			break;
@@ -276,7 +275,7 @@ GLIUInit(struct gliutable *gl){
 			SysmemInit(gl);
 			break;
 	
-		case 	BMO_DMM: /*  check for a DMM entry*/
+		case BMO_DMM: /*  check for a DMM entry*/
 			DMMGL0Init(gl);
 			break;
 	
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index f93109a746..2392775437 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -32,15 +32,20 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 #define RRCF_LOW_CD(base)	RRCF_LOW(base, CACHE_DISABLE)
 
 /* build initializer for P2D MSR */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
-
-
+#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
+#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
+#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12),  .lo=(pmax<<20)|pmin}
+#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin)		\
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
+#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase)			\
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
+#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
+	{msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
+#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
+	{msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
 
 struct msr_defaults {
 	int msr_no;
@@ -63,22 +68,37 @@ const struct msr_defaults  msr_defaults [] = {
 	//{0x1811, .hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)},
 	//{0x1812, .hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)},
 	//{0x1813, .hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)},
-	/* now for GLPCI routing */
+
+	/* GeodeLink Routing */
 	/* GLIU0 */
-	P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
+	/* Traditional Memory 0kB-512kB goes to GLIU port 1, Memory Controller */
+	P2D_BM(0x10000020, 0x1, 0x0, 0x00000, 0xfff80),
+	/* Traditional Memory 512kB-1MB goes to GLIU port 1, Memory Controller */
 	P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(0x1000002c, 0x1, 0x0, 0x0,  0xff03, 0x3),
+	/* Extended Memory, 0xC0000-0x100000, disable write,
+	 * enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
+	 * goest to GLIU Port 1, Memory Controller */
+	P2D_SC(0x1000002c, 0x1, 0x0, 0x0000,  0xff03, 0x3),
 	/* GLIU1 */
-	P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
+	/* Traditional Memory 0kB-512kB goes to GLIU port 1, link to GLIU0 */
+	P2D_BM(0x40000020, 0x1, 0x0, 0x00000, 0xfff80),
+	/* Traditional Memory 512kB-1MB goes to GLIU port 1, link to GLIU0 */
 	P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(0x4000002d, 0x1, 0x0, 0x0,  0xff03, 0x3),
+	/* Extended Memory, 0xC0000-0x100000, disable write,
+	 * enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
+	 * goest to GLIU Port 1, Memory Controller */
+	P2D_SC(0x4000002d, 0x1, 0x0, 0x0000,  0xff03, 0x3),
+	/* end of table */
 	{0}
 };
 
 #define SMM_OFFSET 0x40400000
 #define SMM_SIZE   256
 
-/* we have to do this here. We have not found a nicer way to do it */
+/*
+ * FixME: MSR 0x10000028, 0x40000029 are reprogrammed by SysmemInit()
+ * 0x10000026 and 0x400000023 are reprogrammed by SMMGL0Init() and SMMGL1Init()
+ */
 void
 setup_gx2(void)
 {
@@ -92,7 +112,7 @@ setup_gx2(void)
 	membytes = sizem * 1048576;
 
 	/* we need to set 0x10000028 and 0x40000029 */
-	//	print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
+	//print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
 	msr.hi = 0x20000000 | membytes>>24;
 	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
 	wrmsr(0x10000028, msr);
@@ -100,10 +120,9 @@ setup_gx2(void)
 	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
 	wrmsr(0x40000029, msr);
 	msr = rdmsr(0x10000028);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
 	msr = rdmsr(0x40000029);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
-
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
 
 	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
 	/* calculate the OFFSET field */
@@ -116,7 +135,7 @@ setup_gx2(void)
 	/* calculate the PBASE and PMASK fields */
 	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
 	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
 	msr.hi = tmp;
 	msr.lo = tmp2;
 	wrmsr(0x10000026, msr);
@@ -125,22 +144,22 @@ setup_gx2(void)
 	msr.lo = 0xfbf00100;
 	wrmsr(0x10000028, msr);
 	msr = rdmsr(0x10000028);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
 	wrmsr(0x40000029, msr);
 	msr = rdmsr(0x40000029);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
 
 	msr.hi = 0x2cfbc040;
 	msr.lo = 0x400fffc0;
 	wrmsr(0x10000026, msr);
 	msr = rdmsr(0x10000026);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
 
 	msr.hi = 0x22fffc02;
 	msr.lo = 0x10ffbf00;
 	wrmsr(0x1808, msr);
 	msr = rdmsr(0x1808);
-	//	print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+	//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
 #endif
 	/* now do the default MSR values */