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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 14:12:17 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-28 18:01:01 +0000 |
| commit | ca8968dbc18553d3bea846d4a2001d7fe179cba0 (patch) | |
| tree | b52b43830e4b59b65b1e01ea6af11bd9be2248ac /src/northbridge | |
| parent | 7adfe80469e32e10db0387b395c16d6494a0cd8e (diff) | |
| download | coreboot-ca8968dbc18553d3bea846d4a2001d7fe179cba0.tar.xz | |
nb/intel/ironlake: Drop copy-pasted finalisation steps
This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.
Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/finalize.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 88bc98d2a2..82523f87d6 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -4,19 +4,4 @@ void intel_ironlake_finalize_smm(void) { - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); - - /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; - - /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); } |