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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-03-29 16:21:23 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-01 21:14:08 +0200 |
| commit | d5c82afa37f99a6db8ebb06d0e3c4c0ad4e488db (patch) | |
| tree | 0255dc880cf9136b2d0fce173794d1ff17c995b2 /src/northbridge | |
| parent | 2e1f18336dd4f955e42e8bbe18dbd45b3a3bd85d (diff) | |
| download | coreboot-d5c82afa37f99a6db8ebb06d0e3c4c0ad4e488db.tar.xz | |
northbridge/amd/amdmct: Pack MCT and DCT info structs
This allows safe access of romstage MCT values from ramstage
Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9158
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.h | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0a1f925291..0c6df6c25e 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -260,7 +260,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -}; +} __attribute__((packed)); /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -512,7 +512,7 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; -}; +} __attribute__((packed)); /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 42cca2640b..8e73afe509 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -287,7 +287,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -}; +} __attribute__((packed)); /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sMCTStruct s_C_MCTPtr; struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ -}; +} __attribute__((packed)); /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode) |