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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-11-24 14:11:52 -0600
committerMartin Roth <martinroth@google.com>2016-01-24 23:26:59 +0100
commitdb84a99011bef90c57fcbbd168c95ca6d7aceafd (patch)
tree2f736e24db1a52c760f16db097196ee90646ed83 /src/northbridge
parentad9a2bb0deeab41808a427e2f26420bd24ecb261 (diff)
downloadcoreboot-db84a99011bef90c57fcbbd168c95ca6d7aceafd.tar.xz
nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0 WR value. While this probably had a minimal effect in reality, it should be configured correctly for maximal system stability. Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13147 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 822d813ef1..bcf603139e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -967,7 +967,7 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat,
/* Load data into MRS word */
ret |= (ppd & 0x1) << 12;
- ret |= (wr_ap & 0x3) << 9;
+ ret |= (wr_ap & 0x7) << 9;
ret |= (dll_reset & 0x1) << 8;
ret |= (test_mode & 0x1) << 7;
ret |= ((cas_latency & 0xe) >> 1) << 4;