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authorNico Huber <nico.h@gmx.de>2020-04-26 19:26:36 +0200
committerNico Huber <nico.h@gmx.de>2020-05-27 21:35:06 +0000
commitdfdf102000584e38952122c74858e46fa69acc60 (patch)
treee4b6b08d5a2a6096d51118ed7879bce1b45653e5 /src/northbridge
parent826094f65cf8778bd120e08917ef5557d0bad49d (diff)
downloadcoreboot-dfdf102000584e38952122c74858e46fa69acc60.tar.xz
intel/gma: Don't bluntly enable I/O
The allocator should take care of this. Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/gma.c2
-rw-r--r--src/northbridge/intel/haswell/gma.c2
-rw-r--r--src/northbridge/intel/i945/gma.c8
-rw-r--r--src/northbridge/intel/ironlake/gma.c2
-rw-r--r--src/northbridge/intel/pineview/gma.c2
-rw-r--r--src/northbridge/intel/sandybridge/gma.c2
-rw-r--r--src/northbridge/intel/x4x/gma.c2
7 files changed, 9 insertions, 11 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index e9bd722da9..b48b3c3100 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -154,7 +154,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index ae9e25704d..fa67fe1982 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -464,7 +464,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 181aee56e7..71ed4c42ea 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -674,8 +674,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
- | PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@@ -717,10 +716,9 @@ static void gma_func1_init(struct device *dev)
u32 reg32;
u8 val;
- /* IGD needs to be Bus Master, also enable IO access */
+ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
if (get_option(&val, "tft_brightness") == CB_SUCCESS)
pci_write_config8(dev, 0xf4, val);
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 6de64fb065..6ba95d30fc 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -141,7 +141,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e2d0d18bad..7e5b236bff 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -224,7 +224,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 82e43fc575..6e89b4ef35 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -591,7 +591,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 004960fd8c..69b6f7103d 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -28,7 +28,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */