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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 02:33:59 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 02:33:59 +0000
commite485aa496b2230226abf2255837b9e1d422e9b42 (patch)
tree1991d76df98dd21f6b559084b6b665860ae8ef6d /src/northbridge
parent6fcc961fe846aca897480bb637142d50914a4ea7 (diff)
downloadcoreboot-e485aa496b2230226abf2255837b9e1d422e9b42.tar.xz
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Contemplate the possibility of nbCofVidUpdate not being defined, trying to get closer to BKDG Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdht/AsPsDefs.h2
-rw-r--r--src/northbridge/amd/amdmct/amddefs.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 3907208290..0f6db9fc75 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -229,6 +229,8 @@
/* F3x1F0 Product Information Register */
#define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */
+/* F3x1FC Product Information Register */
+#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */
#define NM_PS_REG 5 /* number of P-state MSR registers */
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 0e7319bb25..92490975ff 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -63,6 +63,7 @@
#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0))
#define AMD_DR_ALL (AMD_DR_Bx)
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
+#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)