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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 00:40:21 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-24 14:29:36 +0000 |
| commit | e4c0555230dd284277dc60c4fbfea6d71a48d2a6 (patch) | |
| tree | 9738756d43331bec5ccaaad13a6c977f6562ed83 /src/northbridge | |
| parent | 1e1515fc9d26a77c088985a22344f6b32d95026a (diff) | |
| download | coreboot-e4c0555230dd284277dc60c4fbfea6d71a48d2a6.tar.xz | |
nb/intel/ironlake: Move southbridge code to ibexpeak
There's no need to set up the southbridge in the northbridge code.
Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 20 |
1 files changed, 1 insertions, 19 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index e6e9ace211..34ae6c1d19 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -15,25 +15,6 @@ static void ironlake_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - /* No reset */ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); - /* halt timer */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); - /* halt timer */ - outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); @@ -112,6 +93,7 @@ void ironlake_early_initialization(int chipset_type) } /* Setup all BARs required for early PCIe and raminit */ + ibexpeak_setup_bars(); ironlake_setup_bars(); s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |