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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-03-13 13:10:29 -0500 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-19 05:00:25 +0100 |
| commit | e9424c593ad4bc3756a4c44e10ea1ec2fab1c3f5 (patch) | |
| tree | 902c08ab1c308bb398540f34977b870383208a34 /src/northbridge | |
| parent | 1e60839be09ee25acea3cf94f5954907c71bb0ad (diff) | |
| download | coreboot-e9424c593ad4bc3756a4c44e10ea1ec2fab1c3f5.tar.xz | |
northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.
Removing this special case does not impact functionality, and paves
the way for early CBMEM support.
Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b144126b..68c6e35d31 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { |