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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 13:51:15 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-09 16:25:43 +0000
commit03f0e43a3c4172941f2eadf30f89413632b90cb4 (patch)
tree8f625362a7b465c8f9e77c22333c0c3b3c181bb8 /src/northbridge
parentf0b5e91b1b76c6034750cfdd45f149cba12aab5e (diff)
downloadcoreboot-03f0e43a3c4172941f2eadf30f89413632b90cb4.tar.xz
haswell: Drop GPIO indirection layers
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/haswell.h1
-rw-r--r--src/northbridge/intel/haswell/romstage.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 1ec4cd1cb9..fa32ecad7c 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -192,7 +192,6 @@ void intel_northbridge_haswell_finalize_smm(void);
struct pei_data;
struct romstage_params {
struct pei_data *pei_data;
- const void *gpio_map;
void (*copy_spd)(struct pei_data *peid);
};
void romstage_common(const struct romstage_params *params);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index c3d9a1088a..8cf2e7ca71 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params)
enable_lapic();
- wake_from_s3 = early_pch_init(params->gpio_map);
+ wake_from_s3 = early_pch_init();
/* Perform some early chipset initialization required
* before RAM initialization can work