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authorStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-02 17:26:33 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-02 18:06:49 +0100
commit1e0ddf6f1fc5a99325155626c02351c388b91101 (patch)
tree459033ab623fc0cd92614a5db57ab38b563054c4 /src/northbridge
parent335ad93965f9c796e105ebd0e004d7185354ffb2 (diff)
downloadcoreboot-1e0ddf6f1fc5a99325155626c02351c388b91101.tar.xz
Fix some issues with new "reference" toolchain
Unfortunately the reference tool chain was updated without ever even testing it on an abuild run. This broke a number of ports. This change gets coreboot at least compiling again for all supported systems. Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1670 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index fd4e2d051d..2f558f5231 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -936,7 +936,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller
*
* NOTE: All cache and stack is lost during ECC scrub loop.
*/
-static void __attribute__((always_inline))
+static inline void __attribute__((always_inline))
initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2)
{
uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;