nb/intel/ironlake: Clean up code style (except raminit)

Reflow lines, correct coding style and align struct members, among
other things. As raminit is very large, handle it on a follow-up.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change.

Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 35 insertions, 38 deletions

diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index 4f221bfe9c..e6e9ace211 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -31,8 +31,7 @@ static void ironlake_setup_bars(void)
 	/* halt timer */
 	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
 	/* halt timer */
-	outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2,
-	     DEFAULT_PMBASE | 0x60 | 0x06);
+	outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
 	printk(BIOS_DEBUG, " done.\n");
 
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
@@ -56,7 +55,7 @@ static void ironlake_setup_bars(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-static void early_cpu_init (void)
+static void early_cpu_init(void)
 {
 	msr_t m;
 
@@ -121,8 +120,7 @@ void ironlake_early_initialization(int chipset_type)
 	elog_boot_notify(s3_resume);
 
 	/* Device Enable */
-	pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,
-			   DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
+	pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
 
 	early_cpu_init();
 
@@ -132,7 +130,7 @@ void ironlake_early_initialization(int chipset_type)
 
 	/* Magic for S3 resume. Must be done early.  */
 	if (s3_resume) {
-		MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
-		MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
+		MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
+		MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
 	}
 }
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 8baccb2831..7d08f3130d 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -152,8 +152,7 @@ static void gma_func0_init(struct device *dev)
 
 		gma_gfxinit(&lightup_ok);
 		/* Linux relies on VBT for panel info. */
-		generate_fake_intel_oprom(&conf->gfx, dev,
-					  "$VBT IRONLAKE-MOBILE");
+		generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
 	} else {
 		/* PCI Init, will run VBIOS */
 		pci_dev_init(dev);
@@ -208,7 +207,7 @@ static const unsigned short pci_device_ids[] = {
 };
 
 static const struct pci_driver gma __pci_driver = {
-	.ops = &gma_func0_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
+	.ops	 = &gma_func0_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
 	.devices = pci_device_ids,
 };
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index 6b631b3114..81bb0e79d7 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -19,16 +19,15 @@ static int bridge_revision_id = -1;
 int bridge_silicon_revision(void)
 {
 	if (bridge_revision_id < 0) {
-		uint8_t stepping = cpuid_eax(1) & 0xf;
-		uint8_t bridge_id =
-		    pci_read_config16(pcidev_on_root(0, 0),
-				      PCI_DEVICE_ID) & 0xf0;
-		bridge_revision_id = bridge_id | stepping;
+		uint8_t stepping = cpuid_eax(1) & 0x0f;
+		uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
+		bridge_revision_id = (bridge_id & 0xf0) | stepping;
 	}
 	return bridge_revision_id;
 }
 
-/* Reserve everything between A segment and 1MB:
+/*
+ * Reserve everything between A segment and 1MB:
  *
  * 0xa0000 - 0xbffff: legacy VGA
  * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
@@ -52,13 +51,12 @@ static void add_fixed_resources(struct device *dev, int index)
 	resource = new_resource(dev, index++);
 	resource->base = (resource_t) 0xfed00000;
 	resource->size = (resource_t) 0x00100000;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
-	  IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
+			  IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
-	mmio_resource(dev, index++, legacy_hole_base_k,
-		      (0xc0000 >> 10) - legacy_hole_base_k);
-	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
-			      (0x100000 - 0xc0000) >> 10);
+	mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
+
+	reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
 
 #if CONFIG(CHROMEOS_RAMOOPS)
 	reserved_ram_resource(dev, index++,
@@ -86,11 +84,11 @@ static const char *northbridge_acpi_name(const struct device *dev)
 #endif
 
 static struct device_operations pci_domain_ops = {
-	.read_resources = pci_domain_read_resources,
-	.set_resources = pci_domain_set_resources,
-	.scan_bus = pci_domain_scan_bus,
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.acpi_name = northbridge_acpi_name,
+	.acpi_name	= northbridge_acpi_name,
 #endif
 };
 
@@ -191,18 +189,18 @@ static void ironlake_init(void *const chip_info)
 }
 
 static struct device_operations mc_ops = {
-	.read_resources = mc_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = northbridge_init,
-	.acpi_fill_ssdt = generate_cpu_entries,
-	.ops_pci = &pci_dev_ops_pci,
+	.read_resources		= mc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= northbridge_init,
+	.acpi_fill_ssdt		= generate_cpu_entries,
+	.ops_pci		= &pci_dev_ops_pci,
 };
 
 static const struct pci_driver mc_driver_ard __pci_driver = {
-	.ops = &mc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x0044,	/* Arrandale DRAM controller */
+	.ops	= &mc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0044,	/* Arrandale DRAM controller */
 };
 
 static struct device_operations cpu_bus_ops = {
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index 4a335d853c..e5ecafe2a2 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -17,7 +17,8 @@
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <southbridge/intel/ibexpeak/me.h>
 
-/* Platform has no romstage entry point under mainboard directory,
+/*
+ * Platform has no romstage entry point under mainboard directory,
  * so this one is named with prefix mainboard.
  */
 void mainboard_romstage_entry(void)
@@ -59,7 +60,8 @@ void mainboard_romstage_entry(void)
 	intel_early_me_status();
 
 	if (s3resume) {
-		/* Clear SLP_TYPE. This will break stage2 but
+		/*
+		 * Clear SLP_TYPE. This will break stage2 but
 		 * we care for that when we get there.
 		 */
 		reg32 = inl(DEFAULT_PMBASE + 0x04);