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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-04 14:23:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:56:06 +0000 |
| commit | 4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch) | |
| tree | e9b31b8b64518a62f6a7885a1de54171471c918b /src/northbridge | |
| parent | 907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff) | |
| download | coreboot-4513020064cc4765e723f6f3cc2b8a45a0dc6545.tar.xz | |
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 7345443c3d..26f49772f8 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -53,9 +53,6 @@ void mainboard_romstage_entry(unsigned long bist) halt (); } - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); |