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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-02 22:55:00 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:16:43 +0000 |
| commit | 5304ce108e1f8fceff543543be092253cf09edb0 (patch) | |
| tree | 3c12a6a8350eac9da4dee56d4065f39496c69ede /src/northbridge | |
| parent | f2e8660fa24b9e153967cc7e01486793806f9779 (diff) | |
| download | coreboot-5304ce108e1f8fceff543543be092253cf09edb0.tar.xz | |
nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chip.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 22 |
2 files changed, 3 insertions, 24 deletions
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 824af3e11d..99d9763241 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -43,11 +43,6 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; - /* - * Maximum PCI MMIO size in MiB. - */ - u16 pci_mmio_size; - /* Data for RAM init */ /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 72621e3cab..c7273ad251 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -338,24 +338,6 @@ void dram_zones(ramctr_timing *ctrl, int training) } } -#define DEFAULT_PCI_MMIO_SIZE 2048 - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} - /* * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. * The ME/PCU/.. has the ability to change this. @@ -382,6 +364,8 @@ bool get_host_ecc_cap(void) return !(reg32 & (1 << 25)); } +#define DEFAULT_PCI_MMIO_SIZE 2048 + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; @@ -389,7 +373,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; - mmiosize = get_mmio_size(); + mmiosize = DEFAULT_PCI_MMIO_SIZE; ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { |