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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-23 03:39:10 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-23 03:39:10 +0000 |
| commit | 53a00b7138fcf65190f33974118dfeb36e9f67cb (patch) | |
| tree | c609fa6c57f91f7cb4a23e2beb0955d6e11b90a6 /src/northbridge | |
| parent | 88fb1a6c371c9f368157bdb907f70d46bb670311 (diff) | |
| download | coreboot-53a00b7138fcf65190f33974118dfeb36e9f67cb.tar.xz | |
match settings per steve goodrich.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index c52277a95a..6ef9d55596 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -67,7 +67,7 @@ sizeram(void) /* ram has none of this stuff */ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) -#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_THROUGH) +#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) #define MSR_WS_CD_DEFAULT (0x21212121) /* 1810-1817 give you 8 registers with which to program protection regions */ |