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| author | Nico Huber <nico.h@gmx.de> | 2021-04-23 15:23:14 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-04-25 13:12:27 +0000 |
| commit | 564413246d7b7ad3972ed5f7d2ba1bb284d3b9ee (patch) | |
| tree | 2678e91d3f956b2dbd3dc4ee0ece096a94e53837 /src/northbridge | |
| parent | 109a9ec339c6c3adc1a3714be46178db13cb8f18 (diff) | |
| download | coreboot-564413246d7b7ad3972ed5f7d2ba1bb284d3b9ee.tar.xz | |
Revert "nb/intel/ironlake: Handle broken ME firmware"
This reverts commit 4447996cc582d2c8745802b84b1f5a635e33a22a.
It looks like the patch repurposed the `memory_reserved_for_heci_mb`
variable as an indicator if the ME firmware is fine. The change to
setup_heci_uma() made it bail out early, even though the implementation
is obviously prepared to set things up even if the requested UMA
size is 0. This also leaves the code in an inconsistent state: The
second if's condition is always true.
Resolves: https://ticket.coreboot.org/issues/305
Change-Id: Ie5a98be3f660078a85a79b5551e86f90f148974f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 8f4aba59da..d8e72b9f1f 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1689,7 +1689,7 @@ static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int he static void setup_heci_uma(struct raminfo *info) { - if (!info->memory_reserved_for_heci_mb || !(pci_read_config32(HECIDEV, 0x40) & 0x20)) + if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20)) return; const u64 heci_uma_addr = @@ -3176,10 +3176,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) ; /* Wait for ME to be ready */ - if (intel_early_me_init() == 0) - info.memory_reserved_for_heci_mb = intel_early_me_uma_size(); - else - info.memory_reserved_for_heci_mb = 0; + intel_early_me_init(); + info.memory_reserved_for_heci_mb = intel_early_me_uma_size(); /* before SPD */ timestamp_add_now(101); |