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| author | Aaron Durbin <adurbin@chromium.org> | 2013-01-08 10:10:33 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-16 04:58:18 +0100 |
| commit | 5c66f08a3a901eb3e1fe6cfd7f22b90cecbf3cf7 (patch) | |
| tree | d31c9f84512dbad8cfdd11f1c470c82bfbf6a705 /src/northbridge | |
| parent | c2c97231e3f36e9d3f1ee8de2394220ec7beadeb (diff) | |
| download | coreboot-5c66f08a3a901eb3e1fe6cfd7f22b90cecbf3cf7.tar.xz | |
haswell: don't add a 0-sized memory range resource
It's possible that TOUUD can be 4GiB in a small physical memory
configuration. Therefore, don't add a 0-size memory range resouce
in that case.
Change-Id: I016616a9d9d615417038e9c847c354db7d872819
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2691
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index d6869c1124..0d611fc105 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -397,7 +397,8 @@ static void mc_add_dram_resources(device_t dev) /* 4GiB -> TOUUD */ base_k = 4096 * 1024; /* 4GiB */ size_k = (unsigned long)(mc_values[TOUUD_REG] >> 10) - base_k; - ram_resource(dev, index++, base_k, size_k); + if (size_k > 0) + ram_resource(dev, index++, base_k, size_k); mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); #if CONFIG_CHROMEOS_RAMOOPS |