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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-29 18:11:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-02 07:16:05 +0000 |
| commit | 694cbc0ddcbe04dbbbb4f97ae4d34861a6ce7054 (patch) | |
| tree | e5255a1e9cb99fcc8f193fb7ac86074816e8254a /src/northbridge | |
| parent | 1d418281e098159339e292c1a4f0dde4bf35122c (diff) | |
| download | coreboot-694cbc0ddcbe04dbbbb4f97ae4d34861a6ce7054.tar.xz | |
{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
Change-Id: I049441dd9074659effc1092dce08224974d60a2c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb788..807ee2a358 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,7 +18,7 @@ static uintptr_t smm_region_start(void) * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return tom & ~((1 << 20) - 1); + return ALIGN_DOWN(tom, 1 * MiB); } void *cbmem_top_chipset(void) |