diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 18:01:35 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-28 18:01:26 +0000 |
| commit | 738331885680b99fadafba92f1cf3e2a76fd8624 (patch) | |
| tree | 273a18ca1471771db97dd04625b69db9a309e143 /src/northbridge | |
| parent | 0cc811789cadb4d0ed2364bc5d7fb926b4e79f7e (diff) | |
| download | coreboot-738331885680b99fadafba92f1cf3e2a76fd8624.tar.xz | |
nb/intel/pineview: Drop MCHBAR macro from DMIBAR access
While the macro value is the same, the DMIBAR register is not HTBONUS1.
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index ce2398496c..89e3ab78c1 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -99,7 +99,7 @@ static void early_misc_setup(void) { MCHBAR32(HIT0); MCHBAR32(HIT0) = 0x00021800; - DMIBAR32(HTBONUS1) = 0x86000040; + DMIBAR32(0x2c) = 0x86000040; pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); |