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authorAaron Durbin <adurbin@chromium.org>2018-09-13 02:10:45 -0600
committerAaron Durbin <adurbin@chromium.org>2018-09-14 08:16:37 +0000
commit75a62e76486f63f6dadb5492c205570ace81e9d5 (patch)
treec3338d2ddd7b2f9f51f35432a24087fc289999fb /src/northbridge
parentcf9ea55473cde8b9a2b9494eca452df7783376e5 (diff)
downloadcoreboot-75a62e76486f63f6dadb5492c205570ace81e9d5.tar.xz
complier.h: add __always_inline and use it in code base
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/raminit.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index b289efe3e1..4919e65ae5 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -24,6 +24,7 @@
* Steven James 02/06/2003
*/
+#include <compiler.h>
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@@ -911,7 +912,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller
*
* NOTE: All cache and stack is lost during ECC scrub loop.
*/
-static inline void __attribute__((always_inline))
+static __always_inline void
initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2)
{
uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;