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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-22 04:37:27 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-22 04:37:27 +0000 |
| commit | 88fb1a6c371c9f368157bdb907f70d46bb670311 (patch) | |
| tree | e15de2e82954df04eeacd055471c278c93b55f4f /src/northbridge | |
| parent | 9d0b30dd2b33d04859986be85b125c3005b2a277 (diff) | |
| download | coreboot-88fb1a6c371c9f368157bdb907f70d46bb670311.tar.xz | |
set up interrupt values for the southbridge, and add a function to
manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions