diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 14:55:18 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-06 10:57:39 +0000 |
commit | 8bf197653fadbb9ca932d0c56bd93f1fb1d4beac (patch) | |
tree | f9c076cacc6ca38af846544d10a98f6a650d4bca /src/northbridge | |
parent | 20905cfe26448166f3224bb59b38dba6cc132274 (diff) | |
download | coreboot-8bf197653fadbb9ca932d0c56bd93f1fb1d4beac.tar.xz |
nb/intel/sandybridge: Deduplicate PCIEXBAR decoding
We can use `decode_pcie_bar` instead, as other northbridges do.
Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/intel/sandybridge/acpi.c | 37 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 |
3 files changed, 7 insertions, 34 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 755d446e97..2c9867480c 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -11,48 +11,19 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - struct device *const dev = pcidev_on_root(0, 0); - - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & (0xffffffffULL << 28); - max_buses = 256; - break; - case 1: /* 128M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 27); - max_buses = 128; - break; - case 2: /* 64M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 26); - max_buses = 64; - break; - default: /* RSVD */ - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, - max_buses - 1); + max_buses - 1); return current; } - static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 8f1db9791b..e670c09cf0 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -40,7 +40,7 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 264d1e2e19..72724a3860 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -177,6 +177,8 @@ void perform_raminit(int s3resume); void report_memory_config(void); enum platform_type get_platform_type(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include <device/device.h> struct acpi_rsdp; |