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| author | Damien Zammit <damien@zamaudio.com> | 2016-07-17 18:26:18 +1000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-19 18:55:50 +0200 |
| commit | b921725b52a98970af5786ca58d7e511fe8870dc (patch) | |
| tree | 2da1eb86d9603ffc0595c5d3e7d4afe421c895f6 /src/northbridge | |
| parent | 47995fbb36d914d96b7c6e49d81135834dc3f157 (diff) | |
| download | coreboot-b921725b52a98970af5786ca58d7e511fe8870dc.tar.xz | |
nb/intel/x4x: Fix CAS latency detection
Fix and use the failsafe CAS detection logic rather than
recalulating the values from raw SPDs.
Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs
(which worked before and still work)
Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15726
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 5d341dbd1e..9be2cd3d73 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -111,10 +111,10 @@ static void sdram_read_spds(struct sysinfo *s) s->dimms[i].chip_capacity = s->dimms[i].banks; s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12; s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9; - s->dimms[i].cas_latencies = 0x78; + s->dimms[i].cas_latencies = 0x70; // 6,5,4 CL s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18]; if (s->dimms[i].cas_latencies == 0) - s->dimms[i].cas_latencies = 7; + s->dimms[i].cas_latencies = 0x70; s->dimms[i].tAAmin = s->dimms[i].spd_data[26]; s->dimms[i].tCKmin = s->dimms[i].spd_data[25]; s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1; @@ -337,10 +337,10 @@ static void sdram_detect_ram_speed(struct sysinfo *s) // Choose max memory frequency for MCH as previously detected freq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz; - // Detect a common CAS latency - commoncas = 0xff; + // Detect a common CAS latency (Choose from 6,5,4 CL) + commoncas = 0x70; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - commoncas &= s->dimms[i].spd_data[18]; + commoncas &= s->dimms[i].cas_latencies; } if (commoncas == 0) { die("No common CAS among dimms\n"); |