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| author | Patrick Georgi <pgeorgi@google.com> | 2014-11-28 22:35:36 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2014-11-30 12:20:07 +0100 |
| commit | bd79c5eaf1f13f33c43c99657f24fa4c0330619a (patch) | |
| tree | c20d6e5e00fcf3494d1c3fdd2d84b97ae34a21ea /src/northbridge | |
| parent | 1b2f2a071488bd15ce80194e85d318cd44659e54 (diff) | |
| download | coreboot-bd79c5eaf1f13f33c43c99657f24fa4c0330619a.tar.xz | |
Replace hlt() loops with halt()
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage_native.c | 3 |
3 files changed, 8 insertions, 11 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1577e68826..197dc0f727 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,11 +20,11 @@ #include <console/console.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); outb(0x6, 0xcf9); - while(1) { - hlt(); - } + halt(); } /* Pass console handler in pei_data */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9de39c6768..de6dac7a2d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -22,11 +22,11 @@ #include <console/usb.h> #include <bootmode.h> #include <string.h> -#include <arch/hlt.h> #include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <halt.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Need reset. */ outb(0x6, 0xcf9); - hlt(); + halt(); } ramctr_timing ctrl; @@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - while (1) { - hlt(); - } + halt(); } memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); } @@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); - hlt(); + halt(); } } diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 902d66d0b9..737cd63c32 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -29,6 +29,7 @@ #include "sandybridge.h" #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> +#include <halt.h> #include "raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" @@ -40,7 +41,7 @@ void main(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); - hlt (); + halt (); } timestamp_init(get_initial_timestamp()); |