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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-26 21:06:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-08-01 12:12:22 +0000 |
| commit | c6e13b6690e15fe32b7c7c135bea5e8a7e6d1753 (patch) | |
| tree | d056606466e378ff6fe576f2a89b6624941718f8 /src/northbridge | |
| parent | 17041207f28f6321cb9fd2b2f87796e3b2fe7b87 (diff) | |
| download | coreboot-c6e13b6690e15fe32b7c7c135bea5e8a7e6d1753.tar.xz | |
nb/intel/x4x: Don't use PCI operations on the pci_domain device
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27245
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 0fcc297639..d1926b29f9 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -44,16 +44,18 @@ static void mch_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); + struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(dev, D0F0_TOUUD); + touud = pci_read_config16(mch, D0F0_TOUUD); touud <<= 20; /* Top of Lower Usable DRAM */ - tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; + tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff; + tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; tom <<= 26; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", @@ -63,7 +65,7 @@ static void mch_domain_read_resources(struct device *dev) /* Graphics memory comes next */ - const u16 ggc = pci_read_config16(dev, D0F0_GGC); + const u16 ggc = pci_read_config16(mch, D0F0_GGC); printk(BIOS_DEBUG, "IGD decoded, subtracting "); /* Graphics memory */ @@ -79,7 +81,7 @@ static void mch_domain_read_resources(struct device *dev) uma_sizek += gsm_sizek; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); - reg8 = pci_read_config8(dev, D0F0_ESMRAMC); + reg8 = pci_read_config8(mch, D0F0_ESMRAMC); reg8 >>= 1; reg8 &= 3; switch (reg8) { |