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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-21 23:24:33 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-21 23:24:33 +0000 |
| commit | cd6985bce39b3aec1ad68235752863ee8da6cd9b (patch) | |
| tree | e5b6f067ddb20fb579a422fd2fac993a7d26fa89 /src/northbridge | |
| parent | 7f809097f86a3196d8c6788a537c0876b3a0df41 (diff) | |
| download | coreboot-cd6985bce39b3aec1ad68235752863ee8da6cd9b.tar.xz | |
vsm can be called now, and then hang.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index fa221e5aea..6dd216fc2a 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -24,7 +24,7 @@ int sizeram(void) { msr_t msr; - int sizem; + int sizem = 0; unsigned short dimm; msr = rdmsr(0x20000018); @@ -131,7 +131,7 @@ setup_gx2_cache(int sizem) val = ((unsigned long long) ROM_PROPERTIES) << 56; /* make rom base useful for 1M roms */ /* fuctory sets this to a weird value, just go with it. */ - val |= ((unsigned long long) 0xff800)<<36; + val |= ((unsigned long long) 0xfff800)<<36; /* set the devrp properties */ val |= ((unsigned long long) DEVICE_PROPERTIES) << 28; /* sigh. Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */ @@ -383,6 +383,8 @@ static void enable_dev(struct device *dev) /* cpubug MUST be called before setup_gx2(), so we force the issue here */ cpubug(); setup_gx2(); + /* do this here for now -- this chip really breaks our device model */ + do_vsmbios(); dev->ops = &pci_domain_ops; pci_set_method(dev); } |